1. Field of the Invention
This invention relates to a semiconductor integrated circuit device with a filter circuit for eliminating a glitch contained in a logic signal.
2. Description of Related Art
It is frequently required of a semiconductor integrated circuit device to eliminate or suppress glitches contained in logic signals to be transferred to internal circuits thereof. A glitch is defined as a transitional voltage spike noise with a narrow pulse width. Therefore, to remove glitches, a filter circuit is used in general. Such the glitch-eliminating filter circuit is usually formed by use of an integral circuit (for example, refer to Japanese Patent Application Laid Open No. 7-336201).
FIG. 5 shows a configuration of a conventional filter circuit 30. This circuit 30 includes two systems of delay circuits 31a and 31b, and an output driver 32 with PMOS transistor P11 and NMOS transistor N11 alternately driven by outputs the delay circuits 31a and 31b. The delay circuit 31a has an inverter chain with inverters I31a, I32a and I33a connected in series to an input node IN, and an integral circuit 32a disposed between the inverters I31a and I32a, which is formed of resistor R11a and capacitor C1a. Similarly, the delay circuit 31b has an inverter chain with inverters I31b, I32b and I33b connected in series to the input node IN, and an integral circuit 32b disposed between the inverters I32b and I33b, which is formed of resistor R11b and capacitor C1b. 
The integral circuits 32a and 32b disposed in the respective delay circuits 31a and 31b serve as low-pass filters (LPF) for eliminating glitches superimposed on input logic signals to be transferred to the internal circuits. In detail, input to the input node IN with level transitions from “L” to “H”, and from “H” to “L”, the logic signals are delayed with certain delay times via the delay circuits 31a and 31b to turn on one of the PMOS transistor P11 and NMOS transistor N11 and turn off the other, whereby delayed logic signals are output at the output node OUT. Positive and negative glitch pulses contained in the input logic signals may be eliminated by the integral circuit 32a and 32b in the delay circuits 31a and 31b. 
However, the conventional glitch eliminating filter circuit, which is formed of a combination of inverters and integral circuit as described above, has such undesirable properties as being not only dependent on power supply voltage variation, but also influenced by threshold voltage variation of transistors in the inverters.